SEG have devoted decades of effort in the area of formal method and verification. Our interested research areas include but not limited to:
1. Cyber physical System Modeling and Verification
2. Real-timed embedded system, timed system, hybrid system, Modeling and Verification
3. Model-based runtime verification of JAVA code
4. Timing analysis of scenario-based specifications
5. Software Verification
6. Formal reasoning of UML
and etc.
We have published lots of papers in related journal and conferences, like
Journal: STVR, JLAP, FAC, STTT, TCJ, IPL, JCST, JOS and etc
Conference: CAV, FMCAD, CHARME, DATE, VMCAI, FORMATS, FORTE, SDL, APSEC, UML, Ada-Europe and etc
|
